Conventionally, there has been a method of utilizing an SOI (Silicon On Insulator) as a most effective means for preventing the digital noise from being fed back into to the analog circuit in a CMOS integrated circuit on which both analog and digital circuits appear. For the SOI, its operational effectiveness is shown in, for example, "A Bonded-SOI-Wafer CMOS 16-bit 50 ksps Delta-Sigma ADC", IEEE 1991, Custom Integrated Circuits Conf. 18. 1.
FIG. 1 illustrates a cross-sectional view of a CMOS integrated circuit using such an SOI arrangement, in which reference numeral 47 denotes a silicon substrate, 48 and 50 each an n-substrate, 49, 51 a p-well formed within the n-substrate, 52 SiO.sub.2, 53, 59 a contact of the n-substrate, 54, 55, 60, 61 a source/drain of a p-channel transistor, 56, 57, 62, 63 a source/drain of an n-channel transistor, 58, 64 a contact of the p-well, 65 through 68 a gate polysilicon, DVDD a digital positive power supply, DVSS a digital negative power supply, AVDD an analog positive power supply and AVSS an analog negative power supply.
If such an SOI arrangement is adopted, since an area constituting the analog circuit (the area comprising the n-substrate 48 and the p-well 49 in FIG. 1) and an area constituting the digital circuit (the area comprising the n-substrate 50 and the p-well 51 of FIG. 1) can be separated with SiO.sub.2 52, the noise feedback from the digital to the analog circuit can be reduced.
However, with the foregoing conventional CMOS integrated circuit using the SOI arrangement, its manufacturing process, which requires bonding and grinding, is complicated, so that it takes much time to manufacture while its manufacturing cost is high.